High-speed processing board

High-speed processing board ・Abundant algorithms available・Highest processing speed in the industry (7,000 pcs/min or higher)・Middleware interfacing the image processing software HALCON and users
  • Features
  • Specifications

Complying with all the CameraLink standards

The high-speed processing board complies with all the CameraLink standards of Base/Medium/Full (2 cameras for Base).

Advantageous high-performance FPGA

I/O board
Image processing by hardware
The high-performance FPGA enables high-speed image processing by the hardware.
Configurable to the algorithm exclusively for the target workpiece
The optimum algorithm exclusively for the target workpiece can be materialized by re-configuring (or resetting) the FPGA circuit by the higher-level PC.
Large image buffer/high-capacity image storage
As general-purpose high-speed memory DDR2SDRAM (So-DIMM) is incorporated in the FPGA circuit, a large buffer/high-capacity image storage of data transferred at high speed becomes possible with PCIe.

Complying with PCI Express 8-Lane

As the board complies with the general-purpose PC expansion buss standard, PCI Express 8-Lane, time to transfer image data to the higher-level PC will drastically be reduced.

With connector for function enhancement

The high-speed serial connector for function enhancement enables direct I/O control directly from the image processing board. It can control the camera shutter, flash, and external devices.

Optimum processing boardcustom-made for customers’requirements

We can offer a diversified product line to comply with customers’ requirements ranging from a medium-scale FPGA to a large-scale FPGA with daughter board.
On the customer’s request, we construct the optimum processing board by selecting the grade of the FPGA and mounting/not mounting the exclusively-designed daughter board.

Product Specifications

Camera CameraLink Full/Medium ×1ch / Base × 2ch
Color/monochrome area/line camera
Up to 85 MHz pixel clock
System bus PCI-Express (x 8)
Image processing memory DDR2 SDRAM 512 MB
Image buffer DDR2 SODIMM ~2GB
Board size H 111.15 × W 177.65
External expansion 120-pin expansion connector for general-purpose I/O interface x 1
40-pin expansion connector for high-speed serial communication x 1
Others Configurable from the higher level (PCI-Express) of FPGA
Complies with serial communication with the camera
I/O Four inputs/Four outputs Open collector
Applicable standard Restriction of Hazardous Supstances
Consumption current 12V 2A
Image processing


Applicable OS Windows XP/Vista/7 (32/64 bit) * Including the future use
SDK configuration mage processing board
Accessory API
Viewer software (including image display, camera control, and camera serial communication functions)
HALCON interface
Accessory API function Image import
Camera control
Camera serial communication(Notes1)
Image buffer(Notes3)
FPGA higher-level configuration(Notes4)
Applicable IDE Microsoft Visual Studio 2005 (C++)
Cooperative software HALCON of MVTec Software GmbH
Image processing library Various filtering
Pattern matching
Many others
  • Notes1)Serial communication can be established with the camera via CameraLink. Parameters set in the camera can be read out, changed, or stored.
  • Notes2)Image clipping function. Only the required area can be read out.
  • Notes3)‘Image import' and ‘image processing’ can be independently executed in the image buffer.
  • Notes4)FPGA can be rewritten via the PCI Express bus.